Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a side contact in a semiconductor device using a double trench process.
Pattern micronization is the core of yield improvement. Mask processes are also requiring smaller sizes due to the pattern micronization. Thus, argon fluoride (ArF) photoresist has been introduced in semiconductor devices at the 40 nm level or less. Yet, the ArF photoresist is reaching the limits as even more micronized patterns are desired.
As a result, a new patterning technology is in demand for memory devices, such as dynamic random access memory (DRAM). Accordingly, a technology for forming a three-dimensional cell has been introduced.
A metal-oxide-semiconductor field effect transistor (MOSFET) having a typical planar channel exhibits physical limitations as to leakage current, power-on current, and short channel effect caused by micronization of a memory device. Thus, it is becoming difficult to further micronize devices. To overcome such difficulties, research has been conducted to develop semiconductor devices using a vertical channel.
A semiconductor device having a vertical channel includes forming an active region having a pillar shape extending vertically from a substrate and surround type gate electrodes, also referred to as vertical gates, enclosing the active region. The semiconductor device having a vertical channel also includes forming junction regions, such as source regions and drain regions, in upper and lower regions of the active region with the gate electrodes at the center. Buried bit lines are coupled to one of the junction regions.
FIG. 1 illustrates a cross-sectional view of a typical semiconductor device including a vertical channel.
Referring to FIG. 1, a plurality of pillar structures are formed over a substrate 11. The pillar structures include active regions 12 and hard mask layers 13 extending in a vertical direction. Gate insulation layers 14 and vertical gates 15 are surrounding outer sidewalls of the active regions 12. Buried bit lines 16 are formed in the substrate 11 by implanting impurity ions. Inter-layer insulation layers 18 are buried over trenches 17 isolating adjacent buried bit lines 16.
However, the typical method shown in FIG. 1 includes implanting dopants by performing an ion implantation process to form the buried bit lines 16. When a semiconductor device is miniaturized, dopant implantation alone may not be satisfactory in reducing a resistance of the buried bit lines 16. Thus, device characteristics may be deteriorated.
Accordingly, a technology for forming buried bit lines with metal layers to reduce a resistance has been recently introduced. In this technology, ohmic-like contacts are formed between active regions and buried bit lines because the buried bit lines include metal layers.
To form ohmic-like contacts, a side contact process which exposes one sidewall of an active region is needed.
A side contact is formed on a portion of one sidewall of an active region to couple the active region and buried bit lines because the height of the buried bit lines is small.
However, as the integration scale increases, the width of active regions has decreased and the depth has deepened. Thus, it has become difficult to form a side contact which selectively exposes one sidewall of an active region. Furthermore, even if side contacts are formed, it is difficult to form the side contacts with an even depth.